1. Field of the Invention
The present invention relates to a system for playing back recorded video information, and more specifically to a system in which the so called special playback modes are enabled with the CLV (constant linear velocity) type disks.
2. Description of Background Information
The present invention relates to a video information playback system, and more specifically to a system for playing a disk-shaped recording medium carrying video information. Such recording media, i.e., video disks are generally classified into two types. One of which is the so called CAV (constant angular velocity) type and the other is the so called CLV (constant linear velocity) type. In disk playing systems adapted for playing both of these two types of disks, it is generally possible to execute special playback modes such as the SLOW mode, the STILL mode, the FAST mode which are performed by the so called track jump operation only when the disk being played is the CAV type.
In other words, these special playback mode operations were not possible with the CLV disks conventionally. The reason of this is as follows.
(1) In the CLV disks, positions of the recording tracks on which the synchronizing signal is recorded are not aligned in a radial direction of the disk, unlike the CAV disks. As a result of this difference, a time base servo control part of the playback system is adversely affected its phase control operation by the track jump operation in the case of the CLV disk. Thus, if a special playback mode is executed with the CLV disk, it is generally very difficult to avoid the fluctuation of time base which is generally of a large magnitude.
(2) Further, in a playback signal produced during a special playback mode, the horizontal synchronizing signal H and a vertical synchronizing signal V become discontinuous. As a result, the horizontal and vertical synchronization operations in a TV monitor system are not properly performed, to cause the rolling of the displayed picture in both horizontal and vertical directions, and generally of large magnitude.
With respect to the problem mentioned in the above paragraph (1), applicants of the present case have already proposed solutions which are described in Japanese Patent Application Nos. 56-197193 (Provisional Publication No. 58-98881) and 59-173716.
The technique described in those patent applications is such that the phase of a reference signal at a time of the completion of the track jump operation with respect to the phase of the synchronizing signal contained in the playback signal is equalized with the phase at a time of the start of the track jump operation. In this way, the disturbance of time base as a result of the jump operations is quickly absorbed.
As for the second problem described in the paragraph (2) of the foregoing description, it is possible to solve the problem using a video memory system (or in other words, a frame synchronizer) which enables the synchronization of synchronizing signals contained in the playback signal with external clock signals. The video memory systems are constructed such that the video signal is transformed into a digital signal using a clock signal which is synchronized with the playback video signal, and the digitalized video sinal is recorded at predetermined locations in a video memory. The recorded digital video signal is then read out by using a stable external clock signal. In this way, the horizontal and the vertical synchronizing signals H and V of the video signal are synchronized with stable synchronizing signals supplied from outside.
FIG. 1 is a block diagram showing an example of such a video memory system.
As shown in this figure, a playback video signal is provided from a disk playing system 1. A write clock signal which is synchronized with the horizontal synchronizing signal or the burst signal of the playback video signal is generated at a write clock signal generating circuit 2 and the video signal is transformed into a digital signal at an A/D (analog to digital) converter 3 using the write clock signal generated by the write clock signal generating circuit 2. The thus obtained serial data are in turn supplied to an S-P register 4 for converting the serial data into parallel data. The operation of the S.fwdarw.P register 4 is such that serial data corresponding to m clocks are converted to parallel data at one time in accordance with a dividing clock signal which is produced at a divider 5 by dividing the above write clock signal by a number m. For instance, if the number m is 8, serial data corresponding to 8 clocks are converted into parallel data at one time. The thus converted parallel data are in turn stored in predetermined address areas of a memory 6.
On the other hand, on reading side, a read clock signal is produced at a read clock signal generating circuit 8 which is synchronized with the horizontal synchronizing signal or the burst signal of a reference synchronizing signal produced at a synchronizing signal generating circuit 7. Data in an address area of the memory 6 which is determined by this read clock signal are read out together, in synchronism with a divided clock signal which is obtained by dividing the read clock signal by a number 8 at a divider 9. Read out parallel data are then transformed into serial data at a P.fwdarw.S register 10, and further converted into an analog signal at an A/D converter 11. The analog signal produced at the A/D converter 11 is provided as an output video signal. In this way, a video signal which is synchronized with the above synchronizing signal can be obtained.
However, a problem which may occur in this circuitry is that the time base (the frequency of the horizontal synchronizing signal and the frequency of the subcarrier signal, and the like) is not necessarily exactly synchronized between the video signal to be stored and the reference synchronizing signal on the reading side. Therefore, there can be a case in which times of writing and reading of data into and from the memory become coincident with each other.
In order to prevent such a problem, there is provided a controller 12 which excecutes the phase control of each clock signal when it is needed, and also control operations are provided so that the serial data on both of input and output sides are processed regularly.
Thus, if video memory systems are utilized, a write clock signal and a read clock signal are required respecitvely for writing and reading quantized digital data into and from the memory unit. Further the control circuit such as the control circuit 12, for controlling the phase of each clock signal at need, is also required. Thus, a number of peripheral circuits are required in conventional video memory systems.
As seen from the above, the special playback mode operation with the CLV disks are not a technically impossible task. However, it is necessary to combine the techniques of quickly absorbing the fluctuation of the time base which is caused by the track jump operation, and employing a video memory for synchronization so as to convert a discontinuous input video signal into a continuous output video signal.
However, by the combination of these prior art techniques, the circuit construction necessarily becomes complicated and large scaled. Therefore, it is not practical to adapt a circuit construction as the above described circuit in consumer products in view of their high cost.